Cadence Design Systems

We are seeking A passionate and motivated EDA test engineer to support the Palladium emulation product line. This position is responsible for verification of the end user’s experience to ensure our products exceed the user’s expectations. There is tremendous opportunity for growth in this position working directly with experts in emulation and acceleration.

Duties:

  • Review Functional Specs and work with the author to improve them.
  • Create and review Test Specs to validate new emulation-software features.
  • Create and review emulation/simulation testcases, including RTL and scripts.
  • Maintain regression runs and results reports.
  • Report product defects, and work with other team members and R&D to debug testcase failures.

Qualifications:

  • BS Degree and a minimum of 7 years of experience in the Design and Verification domains.
  • Expertise in coding and debugging synthesizable designs (RTL) in Verilog.
  • Experience in Verification (design/debug) with Simulation EDA tools (Cadence/Others). Emulation/Hardware Accelerated Verification experience is a plus.
  • Strong communication skills oral and written in team environment.
  • Reviewing features specifications and creating comprehensive verification plans.
  • Designing a regression strategy for test coverage and runtime optimization.
  • Experience in writing programs and shell scripts for test automation.

Plus items:

  • Tool experience: Palladium, Xcelium
  • Language experience: SystemVerilog, VHDL
  • Programming experience: Pearl, Python