中文 English

Cadence

We are specifically focused in developing and enhancing our IP portfolio.

The candidates should have Initial knowledge in at least a subset of the following standard interface protocols, e.g.

PCIe, Ethernet, Flash, DDR, USB, Display, MIPI or other similar protocols
Knowledge of RTL coding in Verilog is essential
Knowledge of how specify, design and develop Individual IP modules, such as UART’s, Memory controllers, Timers etc. is an advantage
Knowledge of coding in System Verilog and System C is an advantage
Knowledge of Synthesis techniques and Timing analysis is an advantage
Knowledge of Emulation and FPGA prototyping methodologies is an advantage
Excellent oral and written English is essential
Minimum BEng Hons 2.1 Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.

For additional details and most recent updates, hit “Apply for job”