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Cadence

In-depth understanding of the ASIC design flow to tapeout including all aspects of Synthesis, Auto Placement and Routing, DFT Scan implementation, Clock Tree implementation, Static Timing Analysis, Logic Equivalence Checking, DRC, LVS, DFM, parasitic extraction flows
Chip level floorplan and integration planning and execution
Creation and management of partitions for soft macros including development of SDC

and more….

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