Hands-on experience with System-Verilog, VHDL, UVM or C/C++ and Metric/Coverage driven verification methodologies.
Experience in front-end (parsing/elaboration and optimization & transformation)  SystemVerilog Compiler development is highly desirable.
Strong knowledge of simulation and verification tools, and direct experience in RTL simulation and simulation acceleration methodologies is desirable.
Excellent communication and leadership skills to work with customers, global RnD, management and sales teams independently.
Strong knowledge of C/C++, data-structures and algorithms required.
Experience with large scale software and distributed processing environments helpful.
Experience with scripting languages such as Python, Tcl or Perl desirable

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