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Cadence

Main technical interface for customer pre and post silicon SOC.
Work closely with Physical design team and RTL team to understand chip architecture, hierarchy.
Perform gate level simulation and RTL simulation to verify functionality.
Support customer Pre-post silicon SOC teams from initial DDR integration and bring-up.
Assist customer with GLS and timing closure.
Drive and support Customer silicon evaluations
Post silicon Validation, testing and characterization of cadence internal silicon test-chips
Own an in-depth cadence silicon test-chip bring-up, functional validation and PVT characterization
Collect structured test measurement data and perform data analysis
Develop and execute comprehensive test plan using high-end equipment (scopes, BERTs)
Participate in validation and characterization of critical sub-blocks like high-speed IOs, DDR Power management system etc.
Develop and optimize comprehensive test automation
Participate in collateral development (characterization reports)
Update DDR teams with the latest customer feedback and competitive analysis.
Work closely with other DDR teams to understand chip architecture, hierarchy and provide feedback on silicon performance, margin to designed specification for helping improve and fine tune IP design

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