Cadence
Design and develop cycle approximate C++/SystemC models for Cadence’s IPs like DDR controller, PCIe controller, etc for use in architectural exploration and performance analysis at different levels – subsystem and SoC level.
– Design and develop protocol specific functional models for various Cadence’s interface IPs like USB, Ethernet, UFS, DP, etc
– Interact with IP designers and architects to understand various IP design/implementation specification and behavior
– Participate in defining traffic patterns, tools and methodology based on the model to help identify functional issues and performance bottlenecks
– Documentation of design specifications, implementation details, FAQ’s, application notes, etc
– Responding to customer cases and reproducing performance issues reported by the customer
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