Expertise on Cadence virtuoso custom/analog layout platform
Knowledge of layout techniques for device matching, minimize parasitics, high speed routing
Good understanding of parasitic RC delay, signal integrity and EM Deep sub-micron cmos layout experience 7nm and smaller geometries
Thorough understanding of layout dependent effects on the circuit and methods of solving advanced layout verification issues on leading foundry flows.
Chip planning and block implementation
Ability to estimate layout schedule for a given circuit, layout planning and provide early feedback to circuit design engineers etc.

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