中文 English

Cadence

As an Application Engineer in Cadence’s Systems Verification Solutions AE team you will be responsible for supporting focus engagements to solve our customer verification challenges with leading edge technologies and methodologies. Your focus will be on Cadence’s Xcelium verification platform. You will support marquee customers in deploying Xcelium on environments with a mix of Verilog, SystemVerilog, SystemC/C/C++, and VHDL using industry standard verification methodologies such as UVM. As an integral part of the account team, you will be involved in account strategy and planning along with delivering customer training, demos and presentations. The role requires driving the future direction of Cadence’s advanced verification methodologies.

 

The ideal candidate will have:

experience with SystemVerilog, VHDL, C/C++ or SystemC
extensive experience with UVM
scripting knowledge (Perl, Python or TCL)
strong HDL design and verification skills
ability to quickly analyze verification environments and design complexity
ability to interact effectively with both external customers and R&D teams
excellent communication, presentation, and interpersonal skills

For more & updated details, hit “Apply for job”