The ideal candidate will have:
•    experience with SystemVerilog, VHDL, C/C++,SystemC or Specman
•    experience with UVM
•    ability to write scripts (Perl, Python or TCL)
•    strong software, HDL design and verification skills
•    ability to quickly analyze verification environments and design complexity
•    ability to interact effectively with both external customers and R&D teams
•    excellent communication, presentation, and interpersonal skills

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