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Cadence

As an Application Engineer in Cadence’s advanced verification solutions AE team you will be responsible for supporting engagements to solve our customer verification challenges with leading edge technologies and methodologies. Your focus will be on Cadence’s Xcelium verification platform.

 

You will support key customers in deploying Xcelium on environments with a mix of Verilog, SystemVerilog, SystemC/C/C++, and VHDL using industry standard verification methodologies such as UVM. As an integral part of the account team, you will be involved in account strategy and planning along with delivering customer training, demos and presentations. The role requires driving the future direction of Cadence’s advanced verification methodologies.

The ideal candidate will have:

·      experience with SystemVerilog, VHDL, C/C++,SystemC or Specman

·      experience with UVM

·      ability to write scripts (Perl, Python or TCL)

·      strong software, HDL design and verification skills

·      ability to quickly analyze verification environments and design complexity

·      ability to interact effectively with both external customers and R&D teams

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