Cadence place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) and experience are required.
Design experience should include ASIC design using industry-standard hardware description languages (Verilog/SystemVerilog)
Demonstrated skills at understanding customer needs and identifying solutions to their challenges with Cadence digital design tools
Exposure to digital IC design and experience in applying solutions in the RTL-GDSII digital space
Demonstrated ability in customer tool debug and usage issues (on-site and remote)
Close collaboration with R&D on issues using established protocols
Communicate with customers on issue workarounds and new tool fixes
Participate in customer benchmark activities and pre-release code bashing with DSG products

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