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Cadence

 

Deep expertise in block level PPA closure on advanced nodes for challenging designs such as ARM cores, CPU/GPU/SOC designs

* Design experience should include ASIC, mixed-signal and low-power design using industry-standard hardware description languages (Verilog)

* Experience in physical implementation of designs at 16nm and below, on actual tapeouts required. Mixed signal experience a plus.

* Cadence or Synopsys syntheis and/or place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) and experience.

* Application Engineer position supporting RTL-to-GDS implementation flows using Innovus Digital Implementation Platform or any other tool.

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