Seeking a highly motivated engineer who can drive improvement to Cadence’s synthesis products from a design perspective. The position provides an excellent opportunity to work closely with the R&D team to define the roadmap of the products.

The candidate should have:

Requires a BS or MS in EE with experience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes.
Prior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis
Understand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes
Industry Experience with Cadence EDA tools in the IC digital implementation flow, preferably on Genus/RC and Innovus/EDI.
Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and Top Level Designs.
Automation skills using Perl, Tcl and shell scripting essential.
Strong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D
Logic design and timing closure skills
Proven track record and experience working in a fast paced environment

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