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Cadence

PHY lead for memory interface IP development for DDR, LPDDR, GDDR, HBM and HBI product lines with a focus on analog design, top level phy planning, timing/jitter and physical design.

Knowledge of analog building blocks such as drivers, receivers, interpolators, delay cells, DLL, PLL, clock trees, reference blocks.

Understanding of timing and jitter budgets and designing custom logic for serialization, FIFOs, timing, clocking structures, data paths,

Multidisciplinary knowledge of IC development disciplines and experience directing teams doing analog mixed signal, RTL development, algorithm and training development, DFT, physical design, ESD and silicon characterization, packaging, boards, signal integrity, power integrity.

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