Cadence

Responsibilities include, but are not limited to the following:

Lead a team of DFT engineers taking a complex ASIC from architecture all the way through productization.
Oversee DFT Gate Level Simulations work and support RTL/PD engineer to correct DFT violations throughout the flow.
Supervise ATPG patterns development to successfully take our ASIC through production.
Participate in ATE bring up, Silicon Debug and Support in system testing within our labs and partners.

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