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Cadence

Required Experience & Qualifications

BSEE and at least 10 years of prior experience required. MSEE and at-least 7 years of prior experience strongly preferred.
Prior experience in RTL design of high-speed logic.
Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.
Knowledge of the IP/SoC level timing closure flow and methodology.
Strong command of Verilog/System Verilog language
Strong command of simulation, lint, synthesis, CDC analysis, STA, formal verification, functional coverage, design for test, and design methodologies
Ability to handle multiple projects/tasks successfully
Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow
Experience in timing constraints generation and management
Proficiency in scripting languages (TCL and Perl)
Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools
Capability to understand and implement improvements to existing methodologies and flows.
Strong background in Constraint analysis and debug, using industry standard tools.
Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing.
Team player with a passion to innovate and can-do attitude.
Self-starter and highly motivated

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