中文 English

Cadence

The Senior Principal FPGA Design Engineer will join a team working on Cadence’s Protium product line’s FPGA development (S1/X1). The team is responsible for FPGA IP architecture, design, verification (simulation), meeting timing after place and route, validation on hardware, characterization of design, release to internal and external customers, debugging internal and external customer’s designs on the hardware. As a Senior FPGA Design Engineer you will be responsible for design, verification (simulation), meeting timing, validation on hardware, characterization of design, debugging on hardware for current products as well as next generation products.

For more & updated details, hit “Apply for job”