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Cadence

We are looking for a motivated individual to work in the DEG (Design Enablement Group) team of the Cadence Tensilica IP. Tensilica has unique technology to build configurable and extensible processor IP. In this team, among other things, we develop methodology and implementation flows that can achieve the best possible PPA (Power, Performance and Area) for these processor IP. We also develop architectural and micro-architectural tools that can be used for power/energy analysis of our processors.

 

Roles and Responsibilities:

Define the features, capabilities of emulation-based power/energy analysis flow as well as system level architecture of the testbench
Develop and maintain synthesizable testbench for configurable Tensilica processors
Run validation tests on specifically/randomly generated processors to ensure the functionality of the flow across different configuration space as well as the different use cases
Design, debug and communicate across the users of this testbench and flow

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