At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Logic Design Engineer for Cadence DDR PHY IP development team.
Position is based in San Jose
The role would include logic design of the DDR PHY IP solution of Cadence.
The work involved will be working on the design, synthesis, timing analysis of the cutting-edge DDR PHY design IP.
The engineer would be responsible to ensure that the design is PD friendly and optimized for best PPA.

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