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Job Title: Lead Design Engineer

Location San Jose, CA

Must haves

7+ Years of Understanding of digital architecture trade-offs for power, performance, and area
Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow.
Experience in SOC design implementation, and production ramp.
Experience using advanced mixed signal verification, and system simulation tools.
IP integration and verification
RTL logic design, debug and functional verification

Job Responsibilities:

Main technical interface between R&D team and tier one customer design teams using advanced high speed PHY IP.
Primary technical contact for customer SOC and system integration questions.
Support customer SOC teams from initial PHY silicon/system integration stages, package/board design, to debug and final production ramp.
Primary technical link between R&D team and global sales teams.
Generate technical specification, data sheets, and application notes.
Update R&D teams with the latest customer feedback and competitive analysis.
Drive and support Customer silicon evaluations and demos.
Work with R&D, Marketing, and sales teams to create technical proposals.
Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus.
Understanding of proper handling of multiple asynchronous clock domains and their crossings
Understanding of Lint checks and proper resolution of errors
Understanding synthesis timing constraints, static timing analysis and constraint development
Understanding of fundamental physical design flows and stages
Exhibit excellent communication skills and be self-motivated and well organized.
Experience with industry standard DFT flows and test methodologies.

Job Requirements:

Must have strong group presentation skills
Ability to clearly communicate technical challenges and status to senior management and executives
Willing to travel