At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

1/ Synthesis/STA design Engineer for Cadence DDR PHY IP development team.

2. Position is based in San Jose

3. The role would include synthesis, STA flow development and support of the same for the DDR PHY IP solution of Cadence.

4. The work involved will be working with the existing synthesis/STA environment, enhancing the flow to support latest technology nodes and supporting Physical design team in implementing the PHY IP
5. The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team


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