Website
Cadence

In-depth understanding of the ASIC design flow to tapeout including all aspects of Synthesis, Auto Placement and Routing, DFT Scan implementation, Clock Tree implementation, Static Timing Analysis, Logic Equivalence Checking, DRC, LVS, DFM, parasitic extraction flows
Chip level floorplan and integration planning and execution
Creation and management of partitions for soft macros including development of SDC
Work on design closure including timing, power, noise, and physical verification
Candidate should have exposure to current nanometer CMOS process technology, ASIC design flow and design methodology challenges and configuration/data management
Architect and develop efficient tools flows and automation around flows as needed

For more details, hit “Apply for job”