Cadence

PHY IP Software Development

 

The high speed SerDes 112 IP group at Cadence architects, designs, and validates wireline transceivers integrated into complex networking SoCs. The ideal candidate for this position will join a team of highly competent developers involved in the design, implementation and verification of mixed signal systems. The successful candidate will build and lead a team of software engineer and be responsible for the PHY API and firmware for multiple DSP-based and analog PHYs, while working closely with the architecture and design team.

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