Cadence

We are looking for experienced DFT engineers to join our design team responsible for test implementation on our next emulation platform.

 

Duties will include:

DFT implementation & verification including Scan, PMBIST, JTAG and other DFT’s related logic.
Scan/PMBIST/JTAG Synthesis Flow co-development with Synthesis engineers.
Generate/Develop and working with PD/STA engineer to verify DFT’s SDC.
Perform DFT gate level simulations work with DFT architecture, and support RTL/PD engineer to correct DFT violations throughout the flow.
Participate in ATE bring up, silicon debug and support in system testing

For more & updated details, hit “Apply for job”