中文 English

Mixel

The candidate should have an MSEE or Ph.D. EE and 15+ years of experience, with expertise in the design of PHY, SerDes, PLL, and CDR circuits. Take overall technical responsibility for multiple exciting, state-of-the-art projects in the fast-growing interconnects IP segment. Direct the creation of the critical components that will interconnect the next generation of mobile, automotive, IoT, and VR platforms. Play a critical part in Mixel’s next phase of growth and contribute to its long-term success. The candidate will lead teams of designers and take overall responsibility for projects’ success. This can be a once-in-a-lifetime opportunity for the right candidate and can rapidly lead to larger responsibilities and rewards.

 

For additional details and most recent updates, hit “Apply for job”