Digital Design Leader – PHY
Design Engineering (ASIC, IP)  Pavia, Italy


Company Description

eSilicon serves the $10B+ ASIC design and manufacturing markets for system OEMs and fabless semiconductor companies.

eSilicon has a world-class custom IP team with a successful track record of first-time silicon success and demonstrated ability to provide differentiated IP cores at leading-edge process nodes.

We are seeking a seasoned, hands-on Digital Design Leader in Pavia, Italy to join this team and define the digital architecture of eSilicon’s HBM PHY and Multi-Channel Die-to-Die PHY products.

Responsibilities include:

· Define and implement the digital architecture of High Bandwidth Memory PHY and Multi-Channel Die-to-Die PHY products

· Work with other design functions to define the specifications, develop the execution plan and schedule, refine the design, and deliver working silicon

· Collaborate with other IP development teams in eSilicon to ensure consistent flows and methodologies

· Work with marketing and customers and participate in standardization committees to understand market trends, industry standards, and the competitive environment for these products

· Work with internal ASIC engineering teams and external customers to ensure their success in using the products

· Mentor the implementation team in digital architecture development to continuously improve their capabilities

Background and Experience Requirements:

BSEE/MSEE plus 10-15 years of experience in the definition of digital system architectures which includes:

· Deep knowledge of a wide range of PHY architectures and DSP algorithms. Specific knowledge of memory interface architectures such as DDR, LPDDR, GDDR, or HBM is considered a plus, as well as specific experience in the fields of Artificial Intelligence and Networking ASICs.

· Advanced knowledge of digital circuit design and optimization (power, timing, area), including RTL development, synthesis, STA, DFT and physical implementation.

· Experience taking designs from the architecture phase through implementation and ultimately product bring-up and validation in silicon.

· Knowledge of languages for modeling, simulating and analyzing dynamical systems (Matlab, Simulink, SystemVerilog, Verilog-A, Verilog-AMS, C, C++).

· Experience with mixed-signal verification is considered a plus.

· Strong lab and silicon validation skills for the evaluation of product and test circuit performance.

· Emphasis on high quality designs and customer deliverables, manufacturability and high product yield.

· Experience establishing and maintaining working relationships with key industry partners and suppliers.

· A strong demonstrated commitment to teamwork and working with internal and external customers.

· Strong communication skills, with the ability to convey complex technical concepts to others in verbal and written form.

· Direct functional management of engineering team(s) or Project Leadership experience

· Well respected by technical colleagues and enjoys mentoring, leading less experienced design engineers.

· Must be eligible to work in Italy without restriction(s).

· Regular travel abroad is required.

· Local candidates given preference (no relocation).

· Only candidates who meet the requirements listed will be considered.