eSilicon

Sr Physical Design Engineers
Design Engineering (ASIC, IP)  Pavia, Italy

Description
eSilicon serves the $10B+ ASIC design and manufacturing markets for system OEMs and fabless semiconductor companies. Our customers have used our products and services to create semiconductor devices for a wide range of end markets. eSilicon offers design and manufacturing services, along with a rich portfolio of customizable memory IP, that makes us an ideal partner for creating semiconductor-based solutions no matter what the end market, no matter what the process node and no matter how fast the expected volume ramp.

Job Description and Key Accountabilities include:
As a member of our team you’ll be responsible for the physical design and optimization of our High Speed Serializer/Deserializer IPs. You will contribute to the development of our market leading products constantly looking for ways to improve our product’s performance, quality and cost. You will work in strict collaboration with our front-end and system design team to develop leading-edge physical implementations and silicon products. You will have the opportunity to expand your experience with physical design tools and flows spanning from RTL to GDS. Your work will focus on the full development flow: Floorplanning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off in conjunction with flow development, innovation and optimization in most advanced CMOS/FinFET technologies.

Education, Experience and Skills Requirements Include:
Master degree in electrical engineering, computer sciences or a comparable qualification
6 years or more of experience in digital design, mixed signal devices integration
Expertise using leading-edge EDA tools for synthesis/implementation and STA (Synopsys, Cadence or Mentor Graphics)
Good knowledge of power flow (power gating, multi-VT flow, power supply management etc.)
Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm (FinFet)
Experience in HDL languages description (SystemVerilog preferred)
Programming-minded with experience using Makefile/Tcl/Perl
Formal Verification tool (Formaility, LEC) is considered a plus
Problem analyzing and solving skills
Excellent verbal and written communication skills (Italian & English)
Must be eligible to work in Country of hire (Italy) without restrictions.

Multiple positions for experienced Engineers exist and levels vary depending on experience.

Only those who meet the qualifications described herein will be considered.