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RESPONSIBILITIES

Verification Engineer involved in functional verification and customer delivery of the EFLX (embedded FPGA) cores in different process nodes (most recent designs in 14/16nm, moving to 7nm and beyond). Responsible for all aspects of verification and emulation including: • Work with Architecture, RTL and Physical Design Engineers • Setup of industry standard Verification IP flow • Point of contact for verification related customer issues and deliverables • Development of verification testbenches and debug for EFLX IP • Functional and GLS verification using Verilog simulator, regressions and coverage closure • JTAG/DFT/ATPG verification and pattern generation • Development of emulation testbenches using standard emulation toolsets (Mentor Graphics’ Veloce, Cadence’s Palladium, etc.) • Development of testbench and debug for silicon validation, post-silicon bring-up and checkout; Linux-based validation using C++/Python or similar • Development of coverage plans and metrics, drive coverage activities and test writing • UPF simulation and debug • Post-Silicon pattern generation and testing using system bench setup to validate EFLX core • Power/Performance benchmarking and debug

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Send your resumes and contact info to hr@flex-logix.com.