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Digital Design Engineer involved in digital and circuit design of EFLX (embedded FPGA) and nnMAX (inference accelerator) cores in 40nm, 28/22nm, 16/12nm, 14/12nm and 7/6nm.

– Responsible for all aspects of silicon design including: o PnR (RTL to GDS) and timing closure for EFLX cores in different process nodes (40nm, 28nm, 16nm, 14nm, 7nm) o optimization of custom digital cell library used for Look Up Tables, DSP and Interconnect switches for optimal performance, power and area (PPA) o timing closure (RTL to GDS) for EFLX/NMAX cores o Timing Verification for EFLX/NMAX cores o EM and IR analysis of EFLX/NMAX cores o DFT/ATPG pattern generation o Validation (testing) of the EFLX/NMAX cores

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