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Hardware Verification Manager or Director


Verification Manager (or Director) involved in functional verification of InferX AI Inference CoProcessor chips, nnMAX Neural Inference cores and EFLX (embedded FPGA) cores in different processes (most recent designs in 14/16nm and moving in 2020 to 7nm)

– Responsible for all aspects of verification and emulation including:

Work closely with Architecture and RTL Design Managers

Setup of industry standard Verification IP flow

Development of verification testbench for EFLX and NMAX IP

Development of verification testbench for silicon validation

DFT/ATPG pattern generation

Functional verification using Verilog simulator

Silicon Testing using bench setup to validate EFLX core

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