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RESPONSIBILITIES

Manage a silicon design team responsible for the digital and circuit design of InferX Inference CoProcessor SoCs in 7nm and beyond. (Our first InferX chip in 16nm is taping out Q4/2019)

– Responsible for all aspects of silicon design management including: o Backend assembly of SOC using nnMAX Inference IP and DDRx memory controller, PCIe IP and timing closure for InferX SOC in 7nm o Global clocks and Power gird o Timing Verification and closure o EM and IR analysis of the SOC o DFT/ATPG and test requirement for nnMAX core o Validation (testing) of the EFLX/nnMAX cores – Technical and people management responsibility – Work with Architecture and front-end design team as well as external Fabs, Design Services groups to support all technical interaction for a successful SoC design.

For more details: https://flex-logix.com/wp-content/uploads/2019/09/2019-09-InferX-SoC-Design-Manager-or-Director.pdf