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Infineon

Job description
In your new role you will:
You will develop the next generation of industry leading, low-power, best-in-class silicon products for the IoT, consumer, and industrial markets.
DFT (Design for Test) engineers on this team play leading roles in ensuring the quality of next generation microcontrollers and IoT processors through structured DFT and Automatic Test Pattern Generation (ATPG) approaches.
DFT engineers on this team collaborate with other company-wide DFT engineers, IP designers, memory designers, and physical implementation engineers to design solutions that satisfy and exceed test and fault coverage requirements while ensuring successful implementation of the design.
Implementing DFT in SoC designs and verifying its functionality
Support of DFT in initial silicon/product debug and production test
Designing and verifying DFT structures for memories (MBIST), digital and analog circuitry
Analyzing and suggesting design changes for Test coverage improvements.
Communicating with IP/SoC designers, Physical Design and Test Engineers on technical issues, input requirements, and deliverables
Scan Implementation for SoCs with wide ranges in size/complexity
MBIST implementation for SoCs with wide ranges in size/complexity
RTL and Gate-level (with and without SDF) simulation DFT logic, ATPG, and MBIST logic
Support DFT aspects of logic synthesis, as well as timing closure support for DFT Test Modes.
Silicon bring-up support and debugging Silicon failure.
Determining and documenting DFT plans for SoC development
Create, simulate and verify automatic generated test patterns (ATPG) and MBIST
Create functional tests and corresponding test patterns

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