中文 English

Infineon

Job description
In your new role you will:
Place & Route of SoCs, IP/blocks, and chip-level partitions. This includes all aspects, including placement, CTS, timing debug, routing, and post-route timing closure to meet power/performance/area requirements.
Run Physical Verification at SoC level and provide guidelines to fix LVS/DRC violations to team members
STA for SoC-level and chip-level partitions
Building full chip floorplan including pin placement, macro placement, power grid.
Generate and Implement ECOs to fix timing, noise, and EM/IR violations.
Participate in continuous improvement and innovation of CAD and physical design methodologies
Assist in flow development for chip integration.

For additional details and most recent updates, hit “Apply for job”