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Infineon

In your new role you will:
Participate in block/chip/system level test plan development and execution
Work with ASIC designers and architects to produce thoroughly verified, robust SoCs, and ensuring subsystems and IPs are properly verified
Oversee verification for the IP/Chip/System and driving functional and code coverage closure
Define verification strategy (Constrained random, Formal, Directed etc.) for IP/Chip/System level verification
Actively participate in cross-functional collaboration with design, software and hardware teams to ensure a successful product delivery

For additional details and most recent updates, hit “Apply for job”