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Infineon

Job description
Main tasks:
This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.
Candidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top.
Candidate will work on various stages of physical design implementation which includes floorplanning, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IRdrop, physical verification checks.
Candidate is expected to have deep understanding and hands-on experience in implementing SOCs with multiple voltage islands, power islands and other power reduction techniques.
Candidate is expected to drive flow/methodology activities to improve upon QoR.

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