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Infineon

Job description
In your new role you will:
Work on the definition and creation of the Design-for-Testability (DfT) concept together with Test Engineering, Quality, Design with regard to manufacturing test coverage, test cost, diagnosability, manufacturability, and yield.
Ensure that a product can be tested and analyzed according to boundary conditions from design, test engineering and customers.
Responsible for the correct implementation and verification of the DfT measures (both standard and project-specific DfT features), i.e. independent implementation, instructions from designers for the installation of measures at block level and ensuring the function of the overall concept.
Implementation of on-chip DfT instruments for test coverage of integrated circuit logic, including logic built-in-self-test (BIST) and memory BIST and repair.
Creation of automatic test pattern generation (ATPG) test patterns to achieve high fault coverage on integrated circuit digital logic and memories.
Verification of test coverage patterns for scan and memory BIST using timing annotated or zero delay logic simulations.
Independent creation of test benches, e.g. for checking special functions of intellectual property on the test system.
Analysis of timing compliance of on chip DfT instruments using static timing analysis (STA) analysis.
Participation in the development of new DfT methods.
Improvement of DfT processes (e.g. generation of test patterns, incorporation of DfT measures into the design) to improve delivery quality and / or reduce test costs.
Specialized experience e.g. in the area of design & test of integrated circuits: IC development (design, test, analysis, verification, layout) as well as IC production (technology, wafer processing, assembly, production test, quality and reliability, yield, logistics).

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