Position: Ph.D./MS NCG position: FPGA HLS C/C++ Device Level programmingKLA is hiring engineers for its Advanced Computing Labs in Chennai, India. KLA ACL is at our new research center in the IITM, Research Park. The goal of the center is to conduct computational research in parallel and distributed sub-systems and deploy them to KLA’s advanced semi-conductor platforms that are used for inspection and metrology tasks in leading fabs. These efforts are part of a larger global initiative at KLA to scale up its AI + HPC + cloud infrastructure.What will you be responsible for?As part of this elite R&D team, the job entails understanding core algorithms that have to expressed in various parallel computing constructs particularly HPC accelerators such as FPGAs.  The first step in optimizing will be to theoretically model break-down of our AI algorithms and model it in terms of available bandwidth, computational FLOPS etc. Historically FPGAs have been programmed in HW RTL languages such VHDL and Verilog. In these projects, one of the main areas of research are to see if newer HLS (Higher Level Synthesis) tools sets such as Xilinx’s Vivaldo/Vitis that allow computation to be expressed in the C/C++ language can be competitive with RTL. The project requires engineers with a very strong background in traditional FPGA programming to map those computations into the HLS C++ language and explore to see how much performance is achieved relative to RTL while enabling significant programmer productivity. While the initial focus of the team will be on lower level module productivity using Vivaldo/Vitis toolsets, it is also the intent to see if one can use higher level programming models such as SYCL/DPC++/TriSycl to achieve similar performance.

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