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As a member of the Design Team for Xtensa processors, you will be responsible for the specification and development of the processor CPU / Memory subsystem modules.  You will design and implement the CPU micro-architecture in Verilog and Tensilica Instruction Extension (TIE), simulate and debug its functions, and run synthesis, place & route, and other EDA scripts to meet timing, area, and power goals.

You will also assist with reviewing test plans, functional diagnostics, debugging failures, and analyzing coverage information.

 

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