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Job Duties:

• Performing activities including: Reading JEDEC standards of memory Protocols, testing them using UVM methodology & simulation & emulation based verification and debug.

• Taking responsibility for product-level model verification.

 

Job Qualifications:

• B.Sc. Electronics or Computer with V. Good with honor (minimum).

• Solid experience with UVM verification methodology and Verilog HDL (2+ years).

• Knowledge of FPGA Design Flow and Digital HW Verification

• A very good communicator in English, proactive, and team player.

Nice To Have:

• Graduation project relates to memory controllers, SoC buses or similar.

• Knowledge of Scripting Languages: Perl/Tcl.

For more details, hit “Apply for job”