中文 English

Mentor Graphics | Siemens

Position: Design and Verification Engineer

About group: Veloce Transactors  (Accelerated Verification IPs)  Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group is responsible for developing transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and expanding further.

Work Experience: 2 to 6 years

Education: (BE/BTech/ME/MTech/MS) from any of the premier engineering institutes.

Roles & Responsibilities:

Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesizable design using verilog/System Verilog.

For more & updated details, hit “Apply for job”