Mentor Graphics | Siemens

We are looking for a highly motivated software engineer to join the R&D team developing Design-for-Test tools as part of the Tessent product line. These advanced tools are part of the industry-leading Tessent platform and are vital for testing and validating ICs that are being built across the semiconductor industry.

The candidate will be responsible for designing and implementing software products/features including writing specifications, planning, schedule estimation, and implementation keeping in mind the project timelines, objectives, and goals. Tessent DFT solutions focus on test insertion and testability analysis not only at the gate-level but at RTL as well. As the complexity of designs keeps on increasing along with shrinking design cycles, there is a trend across the industry to push much of the DFT analysis, insertion, and validations at RTL. Therefore, the candidate should have very good knowledge of RTL and design flows along with C++ programming to develop tools that will work for RTL and gate-level designs. The candidate should be conversant with System Verilog and VHDL so that he/she will be able to develop tools that analyze, introspect, and modify the RTL.

The candidate will be responsible for collaborating with other engineers that are part of the development, quality assurance, technical marketing, technical publications, and customer support teams to enable timely delivery of high quality products.

Self-motivation, ownership of technical problems, results driven positive attitude, solid teamwork, and good communication skills are essential for success within the business unit.

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