中文 English

Website
Mirafra Technologies

Design Verification Engineer

Austin, TX

Job Description: 

·       As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.

·       Triage regression failures and make testbench updates

·       Debug functional errors in RTL model using simulation and debug tools.

·       Maintain efficient and clean regression status

·       Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.

·       Review Architecture and Micro-Architecture specifications.

·       Closely work with Architects and RTL designers.

·       Define, maintain and execute unit level and/or Cluster level verification testplans.

·       Generate and run Testcases on logic simulation models.

·       Code Functional coverage models and System Verilog assertions.

·       Drive Functional Coverage and Code coverage to closure.

·       Integrate C++ reference model into Scoreboards Requirements

Minimum Requirement: 

·       5-15 year’s industry experience in a design verification role.

·       Proficient in System Verilog/UVM/OVM, OOP/C++

·       Knowledge of GPU, experience with Shader, Texture, or Memory System a plus

·       Experience with code coverage and functional coverage driven verification methodology.

·       Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.

·       Excellent working knowledge of scripting languages such as Python or Perl.

If you are interested in the opportunity listed above, please call me ASAP @ 281-624-1110 or send me your resume to anuragbhoi@mirafra.com.
If you aren’t interested, perhaps you know an excellent referral?