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ON SEMICONDUCTOR

·        Physical design verification tasks include creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database. This also includes DFM checks for the advanced node designs.

·        Ensure correct IP and pad-ring integration designs.

·        Also involve in chip planning, floorplanning and power route planning.

Bachelors/Masters with 2-5 years of relevant experience.

For Referral send CV to [email protected]