You will be accountable for inserting DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. In addition, you will Architect, implement, and validate innovative DFT techniques. Furthermore you’ll work closely with adjoining design teams on RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on DFT gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.


For additional details and the most recent updates, hit “Apply for job”