Specific responsibilities will include:
- Design and implementation of Tensilica software tool chain, in particular the instruction set simulator (ISS) for RISC-V processors
- Development of software models for RISC-V processor features for functional, cycle-accurate, and HW/SW simulation.
- Enhancements and maintenance of the existing RISC-V simulator
- Verification of software models in hardware-software co-simulation environment
- Integration of the RISC-V instruction set simulator with 3rd party system modeling environments
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