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proteanTecs

We are looking for the best ASIC Physical Design Engineer to join our team.

Requirements

4+ years experience with RTL2GDS flow
Experience with 4 or more full SoC cycles; taking the design from the RTL phases to GDSII.
Knowledge of Full Flow Cadence and/or Synopsis tools (both flows – advantage).
Excellent debugging skills
Script writing skills with TCL /python /sed/awk

 

Responsibilities

Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Developing Physical design flow for advanced nodes.
Support Field team with customer issues.

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