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Rambus

As a Principal engineer physical design the candidate will have a higher exposure to the management and he/she will be part of major technical decision making. The role gives an opportunity to work on high speed designs in the range of 3.5Ghz. The design requires out of box thinking to meet tighter PPA.

Responsibilities
Lead complete ownership of Bufferchip SOC implementation.
Take complete ownership for Block and SOC implementation depending on the complexity.
Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out  on 22nm nodes or below.
Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
Well versed with the timing closure (STA), timing closure methodologies.

and more

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