As a DFT engineer at Rambus, you will be responsible for design, implementation and verification of all aspects of DFT on complex IPs and chips at advanced process technology nodes viz. 14nm/10/7nm including:Test architecture definition
Identifying and implementing RTL changes for DFT
Developing constraints for scan insertion and test mode timing closure
Scan and ATPG for different fault models
MBIST implementation and verification
Boundary scan, ACJTAG, IEEE 1500 implementation and verification
IEEE1687 (iJTAG) and fault grading for functional manufacturing tests
Running zero delay and timing simulations and debugging on all the above aspects
You will be working on very high speed and low power designs.

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