You will assume both “hands-on” and leadership roles in the design of DDR5 memory buffer chips. You will be responsible for the successful execution of critical chip sub-systems and work in a team through all phases of development including specification, design, verification, and silicon evaluation. The primary focus of the position is transistor-level design of high performance and low power mixed-signal circuits in CMOS, which may include chip IO (Tx/Rx), clock synthesis and distribution (PLL/DLL), adjustable timing circuits (DCDL), voltage regulators, ESD, equalizers, crosstalk cancellation, etc. In addition to analog circuit expertise, job responsibilities include custom logic design, familiarity with static timing analysis, and proficiency in the construction of behavioral models using Verilog and Verilog-A. Furthermore, you will be called upon to both utilize and contribute to the development of tools, scripts, and design flows for robust validation of analog/digital interfaces. Other responsibilities include layout supervision, technical documentation, customer interaction and data preparation, presentation of results and evaluation of peer results in design reviews.

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