中文 English

Rambus

Responsibilities:

Responsible for PDK evaluation, setup, customization, and flows definition
Drive and implement specific Custom Design Automation (CDA) flows such as  Schematic entry, Layout design – color aware and DPT/MPT
Parasitic Extraction for transistor level flow
Device modelling and Simulation environment in Cadence ADE/ADE-XL/Assembler/Explorer
Knowledge and hands-on experience in physical verification – DRC, LVS, DFM checks
Knowledge of Deep Submicron Topics such as LFD, PM, MAS, Litho, etc.
Knowledge of Electrical verification like IREM (VoltusFi/Totem), RelXpert, ERC, PERC
Knowledge of implementing Digital Design Automation (DDA) flows such as RTL2GDS – Synthesis, PNR, CTS, STA, LEC, IREM
Drive Interfacing between Digital and Analog/Mixed signal methodologies.
Develop Custom flows automation, rule deck customizations, improve productivity and efficiency.
Deployment and support of CDA to Design teams.
Debug flow issues and testcases from Design teams for Simulation, LVS, DRC, extraction, IREM, post layout simulation.
Responsible for assisting Tapeouts, final chip finishing runs, interface across foundry/customer for rulesets etc.
Drive and implement methodology projects for productivity and flow enhancement

For additional details and most recent updates, hit “Apply for job”